From d99fb427a28d38756285019d7e70e1b8194595da Mon Sep 17 00:00:00 2001
From: Martin Schwidefsky <schwidefsky@de.ibm.com>
Date: Mon, 18 Dec 2017 07:58:11 +0100
Subject: [PATCH 103/131] s390/spinlock: add osb memory barrier

CVE-2017-5753 (Spectre v1 Intel)

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Andy Whitcroft <apw@canonical.com>
---
 arch/s390/include/asm/barrier.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/s390/include/asm/barrier.h b/arch/s390/include/asm/barrier.h
index 578680f6207a..7c52957a1873 100644
--- a/arch/s390/include/asm/barrier.h
+++ b/arch/s390/include/asm/barrier.h
@@ -7,6 +7,8 @@
 #ifndef __ASM_BARRIER_H
 #define __ASM_BARRIER_H
 
+#include <asm/alternative.h>
+
 /*
  * Force strict CPU ordering.
  * And yes, this is required on UP too when we're talking
@@ -20,6 +22,14 @@
 #define mb() do {  asm volatile("bcr 15,0" : : : "memory"); } while (0)
 #endif
 
+static inline void osb(void)
+{
+	asm volatile(
+		ALTERNATIVE("", ".long 0xb2e8f000", 81)
+		: : : "memory");
+}
+#define osb osb
+
 #define rmb()				mb()
 #define wmb()				mb()
 #define read_barrier_depends()		do { } while(0)
-- 
2.15.1